Porous rf switch for reduced crosstalk

ABSTRACT

A layered structure includes a substrate, a porous layer over the substrate, an epitaxial layer grown directly over the porous layer, and a semiconductor device in the epitaxial layer. The porous layer has a higher resistivity than the substrate. A porosity of the porous layer reduces radio frequency (RF) bleeding from the semiconductor device into the substrate.

CROSS REFERENCES TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.16/742,827, filed Jan. 14, 2020, which claims priority to U.S.Provisional Application No. 62/891,885, filed Aug. 26, 2019, and claimspriority to U.S. Provisional Application No. 62/876,330, filed Jul. 19,2019, which are hereby incorporated herein in their entireties byreference.

BACKGROUND

Substrates based on silicon (Si) for semiconductor devices have becomewidespread for radio-frequency (RF) applications. The continuinginnovation and rapid development of electronics for radio-frequencycommunications increasingly demand smaller and faster semiconductordevices. Increasing performance requires substrate technology thatminimizes RF losses, RF noise, and nonlinear signal distortion. Inparticular, Si-based substrates with high effective resistivities andlow effective permittivities, such as high-resistivity (HR) low-dopedsilicon-on-insulator (SOI) substrates, have been shown to significantlyreduce RF losses, noise, and signal distortion.

However, effective resistivity of HR-SOI substrates depends greatly onthe interface of the Si layer and the buried oxide layer (e.g., SiO₂).Existing effective resistivity for HR-SOI substrates is in the range of20-300 ohm-cm.

A thin porous silicon (pSi) layer inserted between the Si layer and theburied oxide layer of the HR-SOI substrate has demonstrated improved RFperformance with high resistivity of greater than 3000 ohm-cm using pSilayer-based structures with porosity greater than 20% and less than 60%.However, high porosity further reduces the thermal conductivity (e.g.,porosity greater than 20% may reduce thermal conductivity by greaterthan 20%), which can lead to severe degradation of the thermalperformance of a device. Additionally, silicon oxide (SiO₂), apreviously known material for this purpose, is a very poor thermalconductor. Specifically, pure silicon starts with a thermal conductivityof approximately 142 W/m·K depending on the temperature, but the thermalconductivity of silicon oxide (SiO₂) is only approximately 1.5 W/m K,which is barely higher than the thermal conductivity of air, which is 1W/m·K.

SUMMARY

The present disclosure is directed to a layered structure forsemiconductor devices. Specifically, the layered structure includes astarting material layer, and a fully depleted porous layer over thestarting material. According to such a configuration, the layeredstructure improves thermal performance of the device while reducingdegradation.

In some embodiments, the layered structure includes a starting material,such as a silicon substrate. According to an aspect of this embodiment,all or a portion of the starting material may be converted to form aporous layer with tunable electrical properties. Specifically, theporous layer may be tuned to increase the resistivity of the layeredstructure while minimizing the loss of thermal properties. Accordingly,the porous layer may be tuned during the conversion or forming toimprove the thermal performance of the layered structure while reducingdegradation.

According to such a configuration, by carefully tuning the resistivityof a starting material, all or a portion of the starting material can beconverted into a layer with resistivity greater than 10,000 ohm-cm andlow porosity that will deliver excellent resistivity performance whileminimizing the loss of thermal properties. In some aspects of thisembodiment, the layered structure is tuned such that the thermalconductivity is equal to at least 3 watts per meter-Kelvin (W/m·K).

In some embodiments, by carefully tuning the resistivity of a startingmaterial, all or a portion of the starting material can be convertedinto a fully depleted porous layer with an increased bandgap that willdeliver improved performance at high temperature (i.e., no loss ofresistivity during operation).

In some embodiments, the layered structure includes a starting materialand a fully depleted porous layer over the starting material. Accordingto an aspect of this embodiment, the band gap of the fully depletedporous layer is tuned to be greater than the band gap of the startingmaterial.

In some embodiments, the fully depleted porous layer is elementallyidentical to the starting material.

In some embodiments, the layered structure may also include an epitaxiallayer formed over the fully depleted porous layer.

In some embodiments, the epitaxial layer includes at least one ofsilicon, InP, cREO, Mo, AlGaInN, RE-III-N and metal.

In some embodiments, the starting material includes regions of varyingresistivity. For example, the starting material may include a pluralityof regions, with a first region of the starting material having a firstresistivity and a second region of the starting material having a secondresistivity. The first resistivity of the first region may be differentthan the second resistivity of the second region. Additionally, oralternatively, the layered structure may include the fully depletedporous layer over a first region of the starting material and anon-fully depleted porous layer over the second region of the startingmaterial.

In some embodiments, a method of forming the layered structure isprovided. For example, the method includes forming a fully depletedporous layer from a starting material, with a first band gap of thefully depleted porous layer that is greater than a second band gap ofthe starting material.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The present disclosure, in accordance with one or more variousembodiments, is described in detail with reference to the followingdrawings. The drawings are provided for purposes of illustration onlyand merely depict typical or example embodiments. These drawings areprovided to facilitate an understanding of the concepts disclosed hereinand shall not be considered limiting of the breadth, scope, orapplicability of these concepts. It should be noted that for clarity andease of illustration these drawings are not necessarily made to scale.

FIG. 1 shows an example of a layered structure having a fully depletedporous layer formed over a starting material, in accordance with someembodiments of the present disclosure;

FIG. 2 shows an example of a layered structure having a fully depletedporous layer formed over a starting material, where the resistivity ofthe fully depleted porous layer is greater than 10,000 ohm-cm, inaccordance with some embodiments of the present disclosure;

FIG. 3 shows a diagram of sheet resistivity vs. depth for a layeredstructure similar to the structure shown in FIG. 2, in accordance withsome embodiments of the present disclosure;

FIGS. 4-9 show various examples of a layered structure having a fullydepleted porous layer with various starting materials, in accordancewith some embodiments of the present disclosure;

FIGS. 10-13 show various examples of a layered structure having a fullydepleted porous layer of at least two different porosities, inaccordance with some embodiments of the present disclosure;

FIG. 14 shows an example of a layered structure including a fullydepleted porous layer with periodically alternating sublayers formedover the starting material, in accordance with some embodiments of thepresent disclosure;

FIG. 15 shows a diagram of porosity vs. depth of a layered structuresimilar to the structure shown in FIG. 14, in accordance with someembodiments of the present disclosure;

FIG. 16 shows an image of a layered structure having a fully depletedporous layer with periodically alternating sublayers formed over asubstrate, in accordance with some embodiments of the presentdisclosure;

FIG. 17 shows a diagram of sheet resistivity vs. depth for a layeredstructure similar to the structure shown in FIG. 16, in accordance withsome embodiments of the present disclosure;

FIGS. 18-21 show various examples of a layered structure with anepitaxial layer grown on top of the fully depleted porous layer, inaccordance with some embodiments of the present disclosure;

FIG. 22 shows a diagram of experimental data representative of thedifferent thermal conductivities for various examples of a layeredstructure similar to the structure shown in FIG. 1 and a siliconreference, in accordance with some embodiments of the presentdisclosure;

FIG. 23 shows a diagram of photo luminescence vs. energy of the layeredstructure similar to the structure shown in FIG. 1 having band gap Eg1and Eg2, in accordance with some embodiments of the present disclosure;

FIGS. 24 and 25 show diagrams of X-ray diffraction of various examplesof the layered structure having a fully depleted porous layer, inaccordance with some embodiments of the present disclosure;

FIG. 26 shows an example of a layered structure with a fully depletedporous layer over a starting material that includes an additional porouslayer, in accordance with some embodiments of the present disclosure;

FIGS. 27 and 28 show various examples of the additional porous layer ofa layered structure similar to the structure shown in FIG. 26, inaccordance with some embodiments of the present disclosure;

FIG. 29 shows an example of previously known configuration of thelayered structure;

FIG. 30 shows an example of a layered structure with a fully depletedporous layer, in accordance with some embodiments of the presentdisclosure;

FIG. 31 shows an example of a layered structure with a fully depletedporous layer and an RF switch device over the layered structure, inaccordance with some embodiments of the present disclosure;

FIG. 32 shows a diagram of second harmonic distortion of a layeredstructure as compared to previously known structures, in accordance withsome embodiments of the present disclosure;

FIG. 33 shows a diagram of second harmonic distortion of a layeredstructure, in accordance with some embodiments of the presentdisclosure;

FIG. 34 shows a diagram of transmission losses for frequencies up to 20GHz for a radio-frequency switch, in accordance with some embodiments ofthe present disclosure;

FIG. 35 shows a diagram of characteristic impedance for frequencies upto 20 GHz for a radio-frequency switch, in accordance with someembodiments of the present disclosure;

FIG. 36 shows a diagram of second harmonic distortion at differentoperating temperatures for a layered structure similar to the structureshown in FIG. 1, in accordance with some embodiments of the presentdisclosure;

FIG. 37 shows a diagram of effective permittivity vs. frequency forvarious examples of the layered structure, in accordance with someembodiments of the present disclosure;

FIG. 38 shows an example of a layered structure including a fullydepleted porous layer with an acoustic device, in accordance with someembodiments of the present disclosure;

FIG. 39 is a flow diagram of an illustrative process for making alayered structure with a fully depleted porous layer, in accordance withsome embodiments of the present disclosure; and

FIG. 40 is a flow diagram of an illustrative process for making alayered structure with a starting material layer and forming anepitaxial layer, in accordance with some embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The present disclosure is directed to a layered structure that allowsmixed acoustic, photonic and electronic devices to be integrated on thesame platform. For example, the layered structure uses a startingmaterial and a fully depleted porous layer over the starting material,the fully depleted porous layer being tuned to have a resistivitygreater than 10,000 ohm-cm while minimizing thermal conductivity loss.For example, the fully depleted porous layer has a band gap that isgreater than the band gap of the starting material, while also beingelementally identical to the starting material. The layered structureincludes the fully depleted porous layer that is tuned to improve theresistivity of the layered structure while minimizing the loss ofthermal properties. Such configuration permits the layered structure tominimize the loss of thermal properties while reducing degradation ofthe layered structure. In this way, the mixed acoustic, photonic andelectronic devices can be integrated into the layered structure.

In some embodiments, the layered structure may be formed by forming thefully depleted porous layer from a starting material.

In some embodiments, all or a portion of the starting material may beconverted to form a porous layer with tunable electrical properties. Theporous layer may be tuned during the conversion or forming to improveresistivity of the layered structure while maintaining the thermalperformance and reducing degradation of the layered structure.

FIG. 1 shows an example of a layered structure having a fully depletedporous layer, according to an embodiment described herein. The layeredstructure 100 may include a starting material layer 102, on which afully depleted porous layer 104 is formed. According to an aspect ofthis embodiment, the layered structure includes a first band gap, Eg1,of the fully depleted porous layer and a second band gap, Eg2, of thestarting material. The relationship between the band gap of the fullydepleted porous layer (Eg1) and the band gap of the starting material(Eg2) satisfies the following formula: Eg1>Eg2. Stated another way, thefirst band gap, Eg1, of the fully depleted porous layer is greater thanthe second band gap, Eg2, of the starting material.

In some embodiments, the fully depleted porous layer is elementallyidentical to the starting material. That is, the chemical elements inthe starting material are identical to the chemical elements in thefully depleted porous layer of the layered structure.

During the process of forming the layered structure having the fullydepleted porous layer 104 over the starting material layer 102, a layeris formed on top of the starting material that includes a number ofpores with each of the pores having a region around it from which allfree carriers have been removed. Such pores are formed by passing anelectrolyzing current through the starting material from a cathode to ananode. Such process employs a current density of 5-50 mA/cm² and theetch duration is for approximately 10 seconds to 15 minutes. Afterpassing the electrolyzing current through the starting material, a fullydepleted porous layer is formed over the starting material. In theprocess of forming the layered structure, the fully depleted porouslayer is tuned so that the formed fully depleted porous layer may have aresistivity greater than 10,000 ohm-cm, while minimizing the loss of thethermal conductivity of the layered structure by minimizing the numberof pores formed in the layer.

According to some embodiments, the layered structure may be tuned byemploying a starting material with a resistivity in the range of 0.1 to10 ohm-cm, such that all or a portion of the starting material can beconverted into a fully depleted porous layer with high resistivity andlow porosity that will deliver excellent resistivity performance whileminimizing the loss of thermal conductivity of the original startingmaterial. In some aspects of this embodiment, the thermal conductivityof the layered structure is at least equal to 3 watts per meter-Kelvin(W/m·K).

According to such a configuration, by carefully tuning the resistivityof a starting material, all or a portion of the starting material can beconverted into a layer with resistivity greater than 10,000 ohm-cm andlow porosity that will deliver excellent performance while improving thepermittivity of the layered structure. In some aspects of thisembodiment, the permittivity for the layered structure is in a range ofapproximately 2 to 4 farads per meter, as shown in FIG. 37.

According to another embodiment, the fully depleted porous layer has athickness between 10 and 20 μm and a resistivity greater than 10,000ohm-cm.

FIG. 2 shows an example of a layered structure 200 having a fullydepleted porous layer, according to an embodiment described herein. Thelayered structure 200 may include a starting material layer 202, onwhich a fully depleted porous layer 204 is formed. According to anaspect of this embodiment, the layered structure includes a first bandgap, Eg1, of the fully depleted porous layer 204 and a second band gap,Eg2, of the starting material 202. The relationship between the band gapof the fully depleted porous layer 204 and the starting material 202satisfies the formula, Eg1>Eg2. Stated another way, the first band gap,Eg1, of the fully depleted porous layer 204 is greater than the secondband gap, Eg2, of the starting material 102. The fully depleted porouslayer 204 has a thickness between 10 and 20 μm. 100531 FIG. 3 shows adiagram of sheet resistivity vs. depth for the layered structure shownin FIG. 2, according to embodiments described herein. In the diagramshown in FIG. 3, the sheet resistivity of the layered structure with thefully depleted porous layer is plotted against the depth of the layeredstructure. In the layered structure with the fully depleted porouslayer, the sheet resistivity is greater than 10000 ohm-cm between athickness of 0.1 μm and a thickness of 26 μm. The layered structure maybe tuned, such that the starting material 202 having a resistivity of0.1 to 10 ohm-cm is converted to a fully depleted porous layer 204 witha sheet resistivity greater the 10000 ohm-cm. The aforementionedconfiguration permits an increase in resistivity of the fully depletedporous layer while minimizing the loss of the thermal conductivity tofacilitate improved devices.

According to some embodiments, various starting materials may be used inthe layered structure.

FIGS. 4-9 show various examples of a layered structure having a fullydepleted porous layer with various starting materials, according toembodiments described herein. In the example shown in FIG. 4, a startingmaterial 302 having a resistivity of 0.1-10 ohm-cm is employed with afully depleted porous layer 304 formed over the starting material 302.Utilizing a starting material with resistivity of 0.1-10 ohm-cm permitsfor the efficient and cost-effective way of manufacturing the layeredstructure.

In the example shown in FIG. 5, the starting material 302 can include aplurality of sublayers of the starting material. The starting materialincludes a first sublayer 302 a of the starting material having a firstresistivity, Rsh₁ and a second sublayer 302 b of the starting materialhaving a second resistivity, Rsh₂ over the first sublayer 302 a.Further, according to an aspect of this configuration, the startingmaterial 302 may include a plurality of sublayers between the secondsublayer 302 b and a nth sublayer 302 n, which are stacked vertically,where n represents a whole number. The nth sublayer 302 n can becharacterized by a resistivity of Rsh_(n). The layered structure mayhave an interface between starting material layer 302 and fully depletedporous layer 304. This interface may be between the nth sublayer 302 nof the starting material 302 and an adjacent layer (not shown). Theremay be additional layers between the starting material 302 and the fullydepleted porous layer 304.

In the example shown in FIG. 6, the starting material 302 can include aplurality of sublayers of the starting material. The starting materialincludes a first sublayer 302 a of the starting material having a firstresistivity, Rsh₁ and a second sublayer 302 b of the starting materialhaving a second resistivity, Rsh₂ stacked vertically over the firstsublayer 302 a. Further, according to an aspect of this configuration,the starting material 302 may include a third sublayer 302 c with athird resistivity Rsh₃. The third sublayer 302 c being dispose withinthe second sublayer 302 b, with a surface of the third sublayer 302 cbeing disposed at the surface of the second sublayer 302 b. The thirdsublayer 302 c may have an interface with the fully depleted porouslayer 104. This interface may be between the starting material 302 c andan adjacent layer (not shown). There may be additional layers betweenthe starting material 302 c and the fully depleted porous layer 304.

In the example shown in FIG. 7, the starting material 302 d is a siliconsubstrate. The layered structure 300E may have an interface betweenstarting material layer 302 d and fully depleted porous layer 304. Thisinterface may be between the starting material and an adjacent layer(not shown). There may be additional layers between the startingmaterial 302 and the fully depleted porous layer 304.

In the example shown in FIG. 8, the starting material 302 e may includea silicon substrate. The silicon substrate may include a particularcrystal orientation, such as <110> or <100>. The layered structure 300Emay have an interface between layers that is an abrupt rotation incrystal orientation between <100> orientation and a <110> orientation.Alternatively, the layered structure may have an interface betweenlayers that includes a silicon substrate 302 e having a <100>orientation and a fully depleted porous layer 304 having a <100>orientation formed over the silicon substrate 302 e. This interface maybe between the silicon substrate 302 e and an adjacent layer (notshown). This interface may be between the silicon substrate 302 e andthe fully depleted porous layer 304. There may be additional layersbetween the silicon substrate 302 e and the fully depleted porous layer304.

In the example shown in FIG. 9, the starting material 302 f may includea group III-V alloy. The group III-V alloy may include a particularorientation, such as <110> or <100>. The layered structure 300F may havean interface between layers that is an abrupt rotation in crystalorientation between <100> orientation and a <110> orientation.Alternatively, the layered structure may have an interface betweenlayers that includes the group III-V alloy 302 f having a <100>orientation and the fully depleted porous layer 304 having a <100>orientation formed over the group III-V alloy 302 f. This interface maybe between the group III-V alloy 302 f and an adjacent layer (notshown). This interface may be between the group III-V alloy 302 f andthe fully depleted porous layer 304. There may be additional layersbetween the group III-V alloy 302 f and the fully depleted porous layer304.

According to another embodiment, the fully depleted porous layer mayinclude sublayers of periodically alternating sublayers. Theperiodically alternating sublayers may include sublayers with two ormore porosities. In some embodiments, the two alternating porosities maybe a first porosity and a second porosity. In some embodiments, the twoalternating porosities may be a high porosity and a low porosity.Another aspect of this embodiment, the fully depleted porous layer mayinclude three or more sublayers, with each sublayer having a differentporosity. According to such a configuration, the sublayers withdifferent porosities may be stacked vertically over the startingmaterial with the porosity gradually increasing from one end of thefully depleted porous layer to the opposite end of the fully depletedporous layer.

FIGS. 10-13 show various examples of a layered structure having a fullydepleted porous layer of at least two different porosities, according toembodiments described herein. In the example shown in FIG. 10, the fullydepleted porous layer includes a first sublayer 404 a of the fullydepleted porous layer with a first porosity P1, over the startingmaterial 402, and a second sublayer 404 b of the fully depleted porouslayer 404 with a second porosity P2 vertically stacked over the firstsublayer of the fully depleted porous layer 404.

In the example shown in FIG. 11, the fully depleted porous layerincludes a first sublayer 404 b of the fully depleted porous layer 404with a first porosity P2, covering a first region over the startingmaterial 402, and a second sublayer 404 a of the fully depleted porouslayer 404 with a second porosity P1 covering a second region over thestarting material 402 vertically stacked over the first sublayer 404 bof the fully depleted porous layer 404. According to this configurationof this embodiment, the first sublayer and the second sublayer areadjacent to each other and may include an interface between the firstsublayer and the second sublayer. According to another aspect of thisembodiment, there may be a layer between the first sublayer and secondsublayer that acts as a transition layer.

In the example shown in FIG. 12, the fully depleted porous layerincludes a first sublayer 404 a of the fully depleted porous layer witha first porosity P1, covering a first region over the starting material402, and a second sublayer 404 b of the fully depleted porous layer 404with a second porosity P2 covering a second region over the startingmaterial 402. The first sublayer 404 a and the second sublayer 404 bbeing disposed over the starting material 402 and adjacent to each otherin the horizontal direction. According to this configuration of thisembodiment, the first sublayer and the second sublayer are adjacent toeach other and may include an interface between the first sublayer andthe second sublayer. According to another aspect of this embodiment,there may be a layer between the first sublayer and second sublayer thatacts as a transition layer.

In the example shown in FIG. 13, the layered structure includes a toplayer having variety of regions. The top layer includes a fully depletedporous layer at one side and a starting material layer 402 that has notbeen depleted adjacent to the fully depleted porous layer. For example,the top layer includes a fully depleted porous layer 404 on one side ofthe layered structure, a starting material layer 402 adjacent to thefully depleted porous layer and a fully depleted porous layer at anotherside of the top layer. According to this configuration of thisembodiment, the first sublayer and the second sublayer are adjacent toeach other and may include an interface between the first sublayer andthe second sublayer. According to another aspect of this embodiment,there may be a layer between the first sublayer and second sublayer thatacts as a transition layer.

FIG. 14 shows an example of a layered structure 500 including a fullydepleted porous layer 504 with periodically alternating sublayers (504 aand 504 b) formed over a starting material 502. The periodicallyalternating sublayers are stacked vertically over the starting materiallayer 502 and are fully depleted. The periodically alternating sublayers504 may include a plurality of sublayers including a sublayer having afirst porosity 504 a disposed over the starting material 502, a sublayerhaving a second porosity 504 b over the sublayer having the firstporosity 504 a. According to this configuration of the embodiment, thesublayer having the first porosity and the sublayer having a secondporosity can repeat for an n number of times. In some embodiments, thefully depleted porous layer 504 may include between 10 and 20 sublayersthat are periodically alternating sublayers. The layered structure 500may be tuned by varying the periodically alternating sublayers of thefully depleted porous layer 504, which results in an increase inresistivity of the fully depleted porous layer while minimizing the lossof the thermal conductivity of the layered structure 500 to facilitateimproved devices.

The foregoing FIGS. 4-14 are merely illustrative of the principles ofthis disclosure and various modifications may be made by those skilledin the art without departing from the scope of this disclosure. Theembodiments described above are presented for purposes of illustrationand not of limitation. For example, any combination of starting materiallayers and fully depleted porous layers may be used in a layeredstructure in accordance with the present disclosure. In some examples,the starting material of FIG. 4 may be used in combination withconfiguration of the fully depleted porous layer of FIG. 13. Accordingto such a configuration, the layered structure includes a fully depletedlayer and a non-fully depleted layer. In another example, the startingmaterial of FIG. 8 may be used in combination with the fully depletedporous layer of FIG. 11. According to such a configuration, the crystalorientation of the silicone substrate may permit the fully depletedporous layer to form in such a way that the resistivity of the fullydepleted porous layer is increased to provide exceptional performancewhile minimizing the loss of thermal performance of the layeredstructure.

FIG. 15 shows a diagram of porosity vs. depth for a layered structuresimilar to the structure shown in FIG. 14, according to embodimentsdescribed herein. In the diagram shown in FIG. 15, a porosity of thelayered structure is plotted against the depth of the layered structure.In the layered structure, a periodically alternating porosity isobserved for the fully depleted porous layer 504 starting at the surfaceof the fully depleted porous layer 504 and up to the interface betweenthe fully depleted porous layer 504 and the starting material 502, andno porosity is observed for the starting material.

FIG. 16 shows an image of a layered structure having a fully depletedporous layer with periodically alternating sublayers formed over asubstrate, according to embodiments described herein. In the image shownin FIG. 16, the fully depleted porous layer includes periodicallyalternating sublayers with alternating porosities over the substrate(starting material).

In some embodiments, the fully depleted porous layer may include aplurality of sublayers stacked vertically. In some aspects of thisembodiment, the plurality of sublayers may include a graded porosity,such that a sublayer with a high porosity is disposed at a surface ofthe fully depleted porous layer, and a sublayer with a lower porosity isdisposed at an interface of the fully depleted porous layer and thestarting material.

In some embodiments, the fully depleted porous layer may include aplurality of sublayers stacked vertically. In some aspects of thisembodiment, the plurality of sublayers may include a graded porosity.The graded porosity may include a sublayer with a low porosity at oneend of the fully depleted porous layer and a sublayer with a highporosity at an opposite end of the fully depleted porous layer.According to another embodiment, the sublayer with the high porosity maybe disposed at an interface of the fully depleted porous layer and thestarting material, and the sublayer with the low porosity may bedisposed at a surface of the fully depleted porous layer.

FIG. 17 shows a diagram of sheet resistivity vs. depth for a layeredstructure similar to the structure shown in FIG. 16, according toembodiments described herein. In the diagram shown in FIG. 17, the sheetresistivity of the layered structure with the fully depleted porouslayer is plotted against the depth of the layered structure. In thelayered structure with the fully depleted porous layer, the sheetresistivity is greater than 10000 ohm-cm between a thickness of 0.1 μmand a thickness of 5.16 μm, as shown in Table 1. The layered structuremay be tuned, such that the starting material having a resistivity of0.1 to 10 ohm-cm is converted to a fully depleted porous layer with asheet resistivity greater the 10000 ohm-cm. The aforementionedconfiguration permits an increase in resistivity of the fully depletedporous layer while minimizing the loss of the thermal conductivity tofacilitate improved devices.

TABLE 1 Example Sheet Resistivity at varying depths of an examplelayered structure SRP Depth (μm) SRP Resistivity (ohm-cm) 0.00 24,6330.10 24,747 0.19 24,788 0.30 24,448 0.42 23,986 0.49 23,684 0.56 23,5570.60 23,433 0.71 23,186 0.80 22,926 0.91 22,616 0.99 22,199 1.29 20,5791.40 20,512 1.60 20,381 1.91 21,199 2.10 22,652 2.51 24,529 3.01 24,8343.40 24,861 3.70 24,884 4.01 24,909 4.51 24,892 5.01 23,515 5.16 12,371

As shown in Table 1, the sheet resistivity of the layered structure isgreater than 10000 ohm-cm from a depth of 0.0 μm (e.g., surface of thelayered structure) to a depth of 5.16 μm. For example, the layeredstructure is fully depleted and may provide a sheet resistivity greaterthan 20000 ohm-cm from a depth of 0.0 μm (e.g., surface of the layeredstructure) to a depth of 5.16 μm.

According to the aforementioned embodiments, the layered structure canbe obtained with minimal loss of thermal conductivity while theresistance is increased exponentially. The layered structure asdescribed herein, may be tuned to adjust the electrical and thermalproperties. Specifically, the thermal conductivity of the layeredstructure is at least equal to 3 W/m·K.

Additionally or in the alternative, according to some embodiments, thefully depleted porous layer may be lattice matched to the startingmaterial along one crystallographic direction but may be mismatchedalong a second crystallographic direction. Thus, throughout the layeredstructure, the lattice strain between the fully depleted porous layerand the starting material layer is reduced through an interface betweenthe fully depleted porous layer and the starting material layer.

In some embodiments, the periodically alternating sublayers may form anacoustic reflector. In some embodiments, the periodically alternatingsublayers may form a coherent phonon structure.

According to some embodiments, the layered structure may include anepitaxial layer disposed over the fully depleted porous layer. Accordingto some embodiments, the starting material layer may include a siliconsubstrate with fully depleted porous layer formed over the startingmaterial layer. The starting material layer and the fully depletedporous layer being elementally identical. An epitaxial layer may beformed over the fully depleted porous layer. According to someembodiments, the layered structure includes a silicon starting materiallayer, the fully depleted porous layer that is elementally identical tothe silicon starting material layer and the epitaxial layer formed overthe fully depleted porous layer.

FIGS. 18-21 show various examples of a layered structure with anepitaxial layer formed over the fully depleted porous layer, accordingto embodiments described herein. In the example shown in FIG. 18, thelayered structure 700A includes a starting material layer 702, a fullydepleted porous layer 704 over the starting material and an epitaxiallayer 706 over the fully depleted porous layer 704.

In the example shown in FIG. 19, the layered structure 700B includes astarting material layer 702, a fully depleted porous layer 704 formedover the starting material layer 702 and a silicon semiconductor layer706 over the fully depleted porous layer 704. For example, in thelayered structure 700B, the epitaxial layer formed over the fullydepleted porous layer is a silicon semiconductor layer 706. In someembodiments, the layer structure may include the starting materialcomprising a silicon substrate, and the epitaxial layer comprising asilicon layer. The fully depleted porous layer may include a siliconsubstrate as a lower sublayer, a fully depleted silicon layer sandwichedbetween the lower sublayer and a top sublayer of silicon substrate,which is formed by surface sealing the fully depleted porous layer.According to this embodiment, a semiconductor device may be epitaxiallygrown over the fully depleted porous layer. In some embodiments, theepitaxial layer is a silicon semiconductor layer. According to anotherembodiment, the epitaxial layer is a layer comprising one or more of thefollowing InP, cREO, AlGaInN, and RE-III-N compounds. In someembodiments, the semiconductor layer includes silicon and one or more ofthe following InP, cREO, Mo, AlGaInN, RE-III-N compounds and other metalcompounds. According to such a configuration, the layered structure canmaintain the thermal properties of the starting material, whileincreasing the resistivity of the fully depleted porous layer tofacilitate improved semiconductor devices.

In the example shown in FIG. 20, the layered structure 700C includes astarting material layer 702, a fully depleted porous layer 704 over thestarting material, a transitional layer 712 formed over the fullydepleted porous layer 704 and an epitaxial layer 706 formed over thetransition epitaxial layer 712. The transitional epitaxial layer 712 maybe a silicon substrate providing surface sealing of the fully depletedporous layer. Alternatively, the transitional epitaxial layer 712 can bean insulation layer between the fully depleted porous layer and theepitaxial layer 706. According to such a configuration, the layeredstructure can maintain the thermal properties of the starting material,while increasing the resistivity of the fully depleted porous layer tofacilitate improved semiconductor devices.

In the example shown in FIG. 21, the layered structure 700D includes astarting material layer 702, a doping layer 714 over the startingmaterial layer, a fully depleted porous layer 704 over the doping layer,a transitional epitaxial layer 712 formed over the fully depleted porouslayer 704 and an epitaxial layer 706 over the fully depleted porouslayer 704.

In some embodiments, the starting material may be a silicon substratehaving a resistivity of 0.1 to 10 ohm-cm. Utilizing such a substratepermits for the efficient and cost-effective way of manufacturing thelayered structure. The doping layer 714 includes varying silicon dopingconcentrations to permit tuning of the layered structure and provideadditional thermal insulation to the layered structure as whole. Thefully depleted porous layer 704 may include porosity in the range of 5%to 60%. The fully depleted porous layer may have a thickness in therange of 1-50 μm. The transitional epitaxial layer 712 may be a siliconsubstrate providing surface sealing of the fully depleted porous layer704. Alternatively, the transitional epitaxial layer 712 can be aninsulation layer between the fully depleted porous layer 704 andepitaxial layer formed over the transitional epitaxial layer 712. Thetransitional epitaxial layer 712 may have a thickness less of than 10nm. The epitaxial layer 706 may have a thickness in a range of 1 nm to10,000 nm. According to such a configuration, the layered structure canmaintain the thermal properties of the starting material 702, whileincreasing the resistivity of the fully depleted porous layer tofacilitate an improved device. Moreover, this configuration permits thelayered structure to avoid the degradation due to loss of thermalinsulation of the device with resistivity greater than 10,000 ohm-cm.

FIG. 22 shows a diagram of experimental data representative of thedifferent thermal conductivities for various examples for a layeredstructure similar to the structure shown in FIG. 1 and a siliconreference, according to embodiments described herein. In the diagramshown in FIG. 22, thermal conductivity is plotted over time for puresilicon, porous silicon and fully depleted silicon. As shown in the FIG.22, pure silicon starts with a thermal conductivity of approximately 142W/m K depending on the temperature, while porous silicate (pSi) isapproximately 1.5 W/m K. According to the improvements of the presentdisclosure, the fully depleted porous layer exhibits a thermalconductivity of 3 W/m K. The aforementioned configuration permits anincrease in resistivity of the fully depleted porous layer whileminimizing the loss of the thermal conductivity to facilitate improveddevices.

FIG. 23 shows a diagram of photo luminescence vs. energy for a layeredstructure similar to the structure shown in FIG. 1, according toembodiments described herein. In the diagram shown in FIG. 23, photoluminescence is illustrated for the layered structure as the energyincreases, as exemplified by the embodiments of this disclosure. Theaforementioned configuration permits an increase in resistivity of thefully depleted porous layer while minimizing the loss of the thermalconductivity to facilitate improved devices.

FIGS. 24 and 25 show diagrams of X-ray diffraction of various examplesfor a layered structure having a fully depleted porous layer, accordingto embodiments described herein.

FIGS. 26-28 shows various examples of a layered structure with a porouslayer sandwiched between two layers of the starting material, accordingto embodiments described herein. In the example shown in FIG. 26, thelayered structure 1100 includes a starting material layer 1102, a porousmaterial layer 1101 over the starting material, a second layer ofstarting material 1102 over the porous material layer 1101, and a fullydepleted porous layer 1104 over the second layer of starting material.

In the example shown in FIG. 27, the porous material layer 1101 over thestarting material 1102 is shown with a variety of sublayers. The porousmaterial layer 1101 may include a plurality of sublayers. The pluralityof sublayers may be a high and low porous distributed Bragg reflector(DBR). In some embodiments, the plurality of sublayers may include afirst porosity 1101 a and a second porosity 1101 b that alternate backand forth between the starting material. According to such aconfiguration, the layered structure can maintain the thermal propertiesof the starting material, while increasing the resistivity of the fullydepleted porous layer to facilitate improved semiconductor devices.

In the example shown in FIG. 28, the porous material layer 1101sandwiched between the two layers of starting material may be used forwafer cleaving. In such a configuration, the porous material layer mayinclude a buried high porous layer sandwiched between sublayer having alower porosity. According to such a configuration, the layered structurecan maintain the thermal properties of the starting material, whileincreasing the resistivity of the fully depleted porous layer tofacilitate improved devices.

In some embodiments, the layered structure is a layer of aradio-frequency (RF) switch structure.

In some embodiments, the layered structure is a layer of an integratedpassive device.

In some embodiments, the layered structure is a layer of aradio-frequency (RF) filter.

FIG. 29 shows an example of a previously known configuration for alayered structure. In the example shown in FIG. 29, the structureincludes a silicon layer 1202 with a crystal orientation (100), a polysilicon layer 1204, a transition layer (BOX) 1206, a silicon layer 1208with a crystal orientation (100) over the transition layer 1206. Inaddition, a device 1210 may be disposed over the silicon layer 1208.According to such a configuration, the device 1210 may produceradio-frequency field lines 1212 which based on this configuration bleedthrough the poly silicon layer 1204 and into the substrate layer. Thisconfiguration causes significant losses in efficiency.

On the other hand, a configuration employing a fully depleted porouslayer exhibits exceptional sheet resistivity properties and reducesradio-frequency bleeding to the substrate layer. For example, as shownin FIG. 30, an example of a layered structure with a fully depletedporous layer, according to embodiments described herein. The layeredstructure shown in FIG. 30 includes a silicon layer 1302 a with acrystal orientation (100), a fully depleted porous layer 1304 a, asilicon layer 1306 a with a crystal orientation (100) over the fullydepleted porous layer 1304 a. In addition, a device 1308 a may bedisposed over the silicon layer 1306 a. Such a configuration employing afully depleted porous layer exhibits exceptional sheet resistivityproperties and reduces radio-frequency bleeding to the substrate layer.

FIG. 31 shows an example of a layered structure with a fully depletedporous layer and an RF switch device over the layered structure,according to embodiments described herein. In the example shown in FIG.31 a patterned metal is disposed over an oxide layer formed over thefully depleted porous layer. Such patterned metal may be in the form ofa coplanar waveguides or cross-talk devices.

FIG. 32 shows a diagram of second harmonic distortion for a layeredstructure as compared to a previously known structure, according toembodiments described herein. In the diagram shown in FIG. 32, process2A, process 3A, 3B and 4A are exemplary layered structures with fullydepleted porous layers. Further, as can be seen from the variety ofresults, the layered structure may be tuned to improve electricalproperties while minimizing loss of thermal properties.

FIG. 33 shows a diagram of second harmonic distortion for a layeredstructure, according to embodiments described herein.

FIG. 34 shows a diagram of characteristic transmission losses forfrequencies up to 20 GHz for a radio-frequency switch, according toembodiments described herein.

FIG. 35 shows a diagram of characteristic impedance for frequencies upto 20 GHz for a radio-frequency switch, according to embodimentsdescribed herein.

FIG. 36 shows a diagram of second harmonic distortion at differentoperating temperatures for a layered structure similar to the structureshown in FIG. 1, according to embodiments described herein.Specifically, the diagram shows the second harmonic as a function ofpower in (P_(in)) at elevated temperatures.

FIG. 37 shows a diagram of effective permittivity vs. frequency forvarious examples for a layered structure, according to embodimentsdescribed herein. Specifically, the effective permittivity for examplesof the layered structure is in a range of approximately 2 to 4 faradsper meter for frequencies up to 20 GHz.

FIG. 38 an example of a layered structure including a fully depletedporous layer with an acoustic device, according to embodiments describedherein. The layered structure 1800 may include a starting material layer1802, on which a fully depleted porous layer 1804 is formed and anacoustic device 1815 is formed over the fully depleted porous layer1804. According to such a configuration, a flow of acoustic signals1816, travels from the acoustic device 1815 towards the fully depletedporous layer. On the other hand, electrical flow 1814, travels from thesubstrate 1802 towards the fully depleted porous layer 1804. Finally,the thermal flow 1818 travels from the acoustic device through the fullydepleted porous layer and to the substrate.

FIG. 39 is a flow diagram of an illustrative process for making alayered structure with a fully depleted porous layer, in accordance withsome embodiments of the present disclosure. Process 1900 includesforming a fully depleted porous layer from a starting material, with afirst band gap of the fully depleted porous layer is greater than asecond band gap of the starting material. The fully depleted porouslayer is elementally identical to a starting material.

In some embodiments, a starting material is prepared at 1902, in asuitable Dry-in/Dry-out porous silicon tool for forming the layeredstructure. The substrate may include gallium nitride, silicon carbide,sapphire, a silicon wafer, or any other suitable substrate, having apredetermined crystallographic orientation. The substrate may be dopedto adjust the resistivity of the substrate. In some embodiments, thesubstrate may be a silicon wafer, doped with boron to a resistivity ofin the range 0.1-10 ohm-cm. At 1904, the starting material is treated.The treatment is completed in a hydrofluoric acid and de-ionised watermixture having a ratio of (5:2) and surfactant (1 ml/l). At 1906,formation of the fully depleted porous layers on top of the startingmaterial layers is performed by passing electrolyzing current throughthe starting material from cathode to anode. The electrolyzing currentis passed for approximately typically of 10 seconds to 15 minutes. Thecurrent density for the porous formation process is in a range of 5-50mA/cm². At 1908, treating the fully depleted porous layer by postprocessing of the layer. The post processing can include drying thelayer and providing a scaling layer to prepare for application withadditional layers or devices.

FIG. 40 is a flow diagram of an illustrative process for making alayered structure with a starting material layer and forming anepitaxial layer, in accordance with some embodiments of the presentdisclosure. Process 2000 includes forming a fully depleted porous layerfrom a starting material, with a first band gap of the fully depletedporous layer is greater than a second band gap of the starting material.The fully depleted porous layer is elementally identical to a startingmaterial. Further, epitaxially growing a semiconductor layer over thefully depleted porous layer.

In some embodiments, a starting material is prepared at 2002, in asuitable Dry-in/Dry-out porous silicon tool for forming the layeredstructure. The substrate may include gallium nitride, silicon carbide,sapphire, a silicon wafer, or any other suitable substrate, having apredetermined crystallographic orientation. The substrate may be dopedto adjust the resistivity of the substrate. In some embodiments, thesubstrate may be a silicon wafer, doped with boron to a resistivity ofin the range 0.1-10 ohm-cm. At 2004, the starting material is treated.The treatment is completed in a hydrofluoric acid and de-ionised watermixture having a ratio of (5:2) and surfactant (1 ml/l). At 2006,formation of the fully depleted porous layers on top of the startingmaterial layers is performed by passing electrolyzing current throughthe starting material from cathode to anode. The electrolyzing currentis passed for approximately typically of 10 seconds to 15 minutes. Thecurrent density for the porous formation process is in a range of 5-50mA/cm². At 2008, treating the fully depleted porous layer by postprocessing of the layer. The post processing can include drying thelayer and providing a sealing layer to prepare for application withadditional layers or devices. After the fully depleted porous layer istreated, an epitaxial layer may be formed over the fully depleted porouslayer, at 2010.

The growth and/or deposition described herein may be performed using oneor more of chemical vapor deposition (CVD), metalorganic chemical vapordeposition (MOCVD), organometallic vapor phase epitaxy (OMVPE), atomiclayer deposition (ALD), molecular beam epitaxy (MBE), halide vapor phaseepitaxy (HVPE), pulsed laser deposition (PLD), and/or physical vapordeposition (PVD).

As described herein, a layer means a substantially uniform thickness ofa material covering a surface. A layer can be either continuous ordiscontinuous (i.e., having gaps between regions of the material). Forexample, a layer can completely or partially cover a surface, or besegmented into discrete regions, which collectively define the layer(i.e., regions formed using selective-area epitaxy).

Monolithically-integrated means formed on the surface of the substrate,typically by depositing layers disposed on the surface.

Disposed on means “exists on” or “over” an underlying material or layer.This layer may include intermediate layers, such as transitional layers,necessary to ensure a suitable surface. For example, if a material isdescribed to be “disposed on” or “over a substrate,” this can meaneither (1) the material is in intimate contact with the substrate; or(2) the material is in contact with one or more transitional layers thatreside on the substrate.

Single-crystal means a crystalline structure that comprisessubstantially only one type of unit-cell. A single-crystal layer,however, may exhibit some crystalline defects such as stacking faults,dislocations, or other commonly occurring crystalline defects.

Single-domain means a crystalline structure that comprises substantiallyonly one structure of unit-cell and substantially only one orientationof that unit cell. In other words, a single-domain crystal exhibits notwinning or anti-phase domains.

Single-phase means a crystalline structure that is both single-crystaland single-domain.

Substrate means the material on which deposited layers are formed.Exemplary substrates include, without limitation: bulk gallium nitridewafers, bulk silicon carbide wafers, bulk sapphire wafers, bulkgermanium wafers, bulk silicon wafers, in which a wafer comprises ahomogeneous thickness of single-crystal material; composite wafers, suchas a silicon-on-insulator wafer that comprises a layer of silicon thatis disposed on a layer of silicon dioxide that is disposed on a bulksilicon handle wafer, or the porous germanium, germanium over oxide andsilicon, germanium over silicon, patterned germanium, germanium tin overgermanium, and/or the like; or any other material that serves as baselayer upon which, or in which, devices are formed. Examples of suchother materials that are suitable, as a function of the application, foruse as substrate layers and bulk substrates include, without limitation,alumina, gallium-arsenide, indium-phosphide, silica, silicon dioxide,borosilicate glass, and pyrex. A substrate may have a single bulk wafer,or multiple sub-layers. Specifically, a substrate (e.g., silicon,germanium, etc.) may include multiple non-continuous porous portions.The multiple non-continuous porous portions may have different densitiesand may be horizontally distributed or vertically layered.

Miscut Substrate means a substrate which comprises a surface crystalstructure that is oriented at an angle to that associated with thecrystal structure of the substrate. For example, a 6° miscut <100>silicon wafer comprises a <100> silicon wafer that has been cut at anangle to the <100> crystal orientation by 6° toward another majorcrystalline orientation, such as <110>. Typically, but not necessarily,the miscut will be up to about 20°. Unless specifically noted, thephrase “miscut substrate” includes miscut wafers having any majorcrystal orientation. That is, a <111> wafer miscut toward the <011>direction, a <100> wafer miscut toward the <110> direction, and a <011>wafer miscut toward the <001> direction.

Semiconductor refers to any solid substance that has a conductivitybetween that of an insulator and that of most metals. An examplesemiconductor layer is composed of silicon. The semiconductor layer mayinclude a single bulk wafer, or multiple sub-layers. Specifically, asilicon semiconductor layer may include multiple non-continuous porousportions. The multiple non-continuous porous portions may have differentdensities and may be horizontally distributed or vertically layered.

A first layer described and/or depicted herein as “configured on,” “on,”“formed over,” or “over” a second layer can be immediately adjacent tothe second layer, or one or more intervening layers can be between thefirst and second layers. A first layer that is described and/or depictedherein as “directly on” or “directly over” a second layer or a substrateis immediately adjacent to the second layer or substrate with nointervening layer present, other than possibly an intervening alloylayer that may form due to mixing of the first layer with the secondlayer or substrate. In addition, a first layer that is described and/ordepicted herein as being “on,” “over,” “directly on,” or “directly over”a second layer or substrate may cover the entire second layer orsubstrate, or a portion of the second layer or substrate.

A substrate is placed on a substrate holder during layer growth, and soa top surface or an upper surface is the surface of the substrate orlayer furthest from the substrate holder, while a bottom surface or alower surface is the surface of the substrate or layer nearest to thesubstrate holder. Any of the structures depicted and described hereincan be part of larger structures with additional layers above and/orbelow those depicted. For clarity, the figures herein can omit theseadditional layers, although these additional layers can be part of thestructures disclosed. In addition, the structures depicted can berepeated in units, even if this repetition is not depicted in thefigures.

From the above description it is manifest that various techniques may beused for implementing the concepts described herein without departingfrom the scope of the disclosure. The described embodiments are to beconsidered in all respects as illustrative and not restrictive. Itshould also be understood that the techniques and structures describedherein are not limited to the particular examples described herein, butcan be implemented in other examples without departing from the scope ofthe disclosure. Similarly, while operations are depicted in the drawingsin a particular order, this should not be understood as requiring thatsuch operations be performed in the particular order shown or insequential order, or that all illustrated operations be performed, toachieve desirable results.

What is claimed is:
 1. A layered structure comprising: a substrate; aporous layer over the substrate, the porous layer having a higherresistivity than the substrate; an epitaxial layer grown directly overthe porous layer; and a semiconductor device in the epitaxial layer,wherein a porosity of the porous layer reduces radio frequency (RF)bleeding from the semiconductor device into the substrate.
 2. Thelayered structure of claim 1, wherein the porosity of the porous layeris between about 35% and about 65%.
 3. The layered structure of claim 1,wherein the porous layer is a fully depleted porous layer that is freeof carriers.
 4. The layered structure of claim 1, wherein the porosityof the porous layer is graded with a higher porosity adjacent to aninterface with the substrate than a porosity adjacent to an interfacewith the epitaxial layer.
 5. The layered structure of claim 1, whereinthe semiconductor device comprises a transistor of a radio frequency(RF) switch.
 6. The layered structure of claim 1, wherein the substrateis a silicon wafer or a 111-V semiconductor wafer.
 7. A layeredstructure comprising: a substrate; a porous layer over the substrate,the porous layer having a higher resistivity than the substrate; anepitaxial layer grown directly over the porous layer; and a transistorof a radio frequency (RF) switch in the epitaxial layer, wherein aporosity of the porous layer reduces radio frequency (RF) bleeding fromthe transistor into the substrate.
 8. The layered structure of claim 7,wherein a second harmonic distortion of the layered structure is lessthan about −120 dBm at P_(in)=15 dBm.
 9. The layered structure of claim8, wherein the second harmonic distortion of the layered structure isless than about −140 dBm at P_(in)=15 dBm.
 10. The layered structure ofclaim 7, wherein a transmission loss of the layered structure is lessthan about 0.2 dB/mm.
 11. A method comprising: forming a porous layerover a wafer, the porous layer having a higher resistivity than thewafer; growing an epitaxial layer directly over the porous layer; andforming a semiconductor device in the epitaxial layer, wherein aporosity of the porous layer reduces radio frequency (RF) bleeding fromthe semiconductor device into the wafer.
 12. The method of claim 11,wherein forming the porous layer comprises forming the porous layer overan entirety of the wafer.
 13. The method of claim 11, wherein formingthe porous layer comprises a dry-in and dry-out porosification process.14. The method of claim 13, wherein the dry-in and dry-outporosification process comprises: exposing the wafer to an acidsolution; passing an electrolyzing current through the wafer and theacid solution to form the porous layer; and drying the porous layer. 15.The method of claim 11, wherein the semiconductor device comprises atransistor of a radio frequency (RF) switch.
 16. The method of claim 11,further comprising annealing the porous layer prior to growing theepitaxial layer.
 17. The method of claim 11, wherein growing theepitaxial layer comprises growing the epitaxial layer with a crystalorientation that matches a crystal orientation of the wafer.
 18. Themethod of claim 11, wherein the porosity of the porous layer is betweenabout 35% and about 65%.
 19. The method of claim 11, wherein forming theporous layer comprises porosifying an upper portion of the wafer. 20.The method of claim 11, wherein the wafer comprises a silicon wafer.